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riscv-software-src / riscv-isa-sim

Spike, a RISC-V ISA Simulator
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Some bitmanip instruction function in spike #1421

Open alextxia13 opened 1 year ago

alextxia13 commented 1 year ago

For RISC-V Bit-Manipulation ISA-extensions spec, rori, binvi, bclri bseti and bexti instructions have different encoding in RV64 and RV32. In the spec, it said for RV32, the encodings corresponding to shamt[5] =1 are reserved. How does spike work in this situation? I see in rori.h, it requires (SHAMT > xlen) which means it will cause exception if shamt[5] =1. But in binvi, bclri bseti and bexti, it will not raise any exceptions. It seems that shamt[5] =1 is ignored. It is a little confused when the spike executes the instruction.

aswaterman commented 1 year ago

This might be an omission. It's technically not a bug, because raising illegal-instruction exceptions on reserved encodings is only recommended, not required. But I don't think that was our intent in this case. If you'd like to make a PR that makes these instructions match rori, we'd accept it.