fmvh.x.d in RV32 need be sign-extended

riscv-software-src / riscv-isa-sim

Spike, a RISC-V ISA Simulator

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Open Madman-Hugo opened 9 months ago

Madman-Hugo commented 9 months ago

For implementation of fmvh_x_d, when write back， the result should be sign-extended

WRITE_RD(ui.ui >> 32);

aswaterman commented 9 months ago

Yeah, it’s missing a sext32() call. Can you make a PR?