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riscv-software-src / riscv-isa-sim

Spike, a RISC-V ISA Simulator
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Spike behavior: Mask register overlaps source register #1545

Open ajayvreddy opened 9 months ago

ajayvreddy commented 9 months ago

I have the following instruction which uses V0 as destination and also as mask

core   0: 0xffffa1000010b0e0 (0xb00540d7) vnsrl.wx v1, v0, a0, v0.t
core   0: 0 0xffffa1000010b0e0 (0xb00540d7) c8_vstart 0x0000000000000000 e8 mf4 l8

I see there was spec update:

A vector register cannot be used to provide source operands with more than one EEW for a single instruction. A mask register source is considered to have EEW=1 for this constraint. An encoding that would result in the same vector register being read with two or more different EEWs, including when the vector register appears at different positions within two or more vector register groups, is reserved.

This would mean mask register v0 cannot overlap with source registers as well.

scottj97 commented 9 months ago

It's not clear what the expected behavior vs actual behavior is. My guess:

Expected behavior: illegal instruction trap Actual behavior: no illegal instruction trap

Is that right?

ajayvreddy commented 9 months ago

Yes. I'm expecting it to take a fault (acc to the new spec)

aswaterman commented 9 months ago

cc @chihminchao

ajayvreddy commented 9 months ago

Hi @chihminchao can you please help with this...