riscv-software-src / riscv-isa-sim

Spike, a RISC-V ISA Simulator
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Why does my custom instruction simulation run incorrectly? #1636

Open niuzhi1221 opened 7 months ago

niuzhi1221 commented 7 months ago

After seeing this C function: double clamp (double x ) { return x < 0 ? 0 : x > 1 ? 1 : x ; } I want to design a custom instruction named 'clp' , it uses F extesnion. The instruction format I designed is as follows: clp rd rs1 rs2 rs3 rm 26..25=1 6..2=0x15 1..0=3 First , I add the MASK_CLP and MATCH_CLP to riscv-gnu-toolchain/riscv-binutils /include/opcode/riscv-opc.h. Then, in riscv-gnu-toolchain/riscv-binutils/opcodes/riscv-opc.c I add the following content: {"clp", 0, INSN_CLASS_D_INX, "D,S,T,R", MATCH_CLP|MASK_RM, MASK_CLP|MASK_RM, match_opcode, 0}, {"clp", 0, INSN_CLASS_D_INX, "D,S,T,R,m", MATCH_CLP, MASK_CLP, match_opcode, 0}, After that , I recompiled my toolchain. To achieve command functionality, I want to simulate the clp instruction in Spike.So I firstly add MATCH_CLP and MASK_CLP in spike/riscv/encoding.h, then I make a file named clp.h in spike/riscv/insns, I add the following content: require_either_extension('D', EXT_ZDINX); require_fp; softfloat_roundingMode = RM; if(f64_lt(FRS1_D, FRS2_D)){ WRITE_FRD_D(FRS1_D); } else if(f64_lt(FRS3_D,FRS1_D)){ WRITE_FRD_D(FRS3_D); } else WRITE_FRD_D(FRS2_D); set_fp_exceptions; Then , in spike/riscv/riscv.mk.in file, I add this: image in spike/disasm/disasm.cc file , I add this: image Then I recompiled my spike. I write a test C program named clamp.c: image But I can't use command spike pk clamp to simulate it:

image Sincerely looking forward to your help!

baul-iisc commented 3 months ago

Hello niuzhi1221, You could able to resolve the issue? Actually I am also trying to implement some custom instructions, but not able to figure it out after adding these custom instructions how to execute my targeted workload using these custom instructions. It will be really helpful if you have figured it our and guide me to implement it.