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riscv-software-src / riscv-isa-sim

Spike, a RISC-V ISA Simulator
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mcontrol6.timing bit is set #1651

Open JAYANTH-IITM opened 4 months ago

JAYANTH-IITM commented 4 months ago

While trying to implement type 6 trigger (mcontrol6) with load bit enabled according to the debug spec 1.0 but spike doesnt seem to support (still using 0.13 version) . tinfo.version == 0 , implies implementation of older debug spec.This issue is persistent also after updating to latest version of spike , openocd and riscv-tests.After the checking the log (attached below) , dmstaus.version == 2 , which according to latest spec , means version 0.13. Expected to implement in version 1.0 debug spec ( dmstatus.version == 3). PFA , log after updating spike and openocd .

20240424-122230-spike32-TriggerDmode.log

JAYANTH-IITM commented 4 months ago

@aswaterman , please guide here .

aswaterman commented 4 months ago

Sorry, I don't maintain debug support in Spike. Perhaps @timsifive can comment.

JAYANTH-IITM commented 4 months ago

Thanks for the referring .

rtwfroody commented 4 months ago

I'll take this on.