riscv-software-src / riscv-isa-sim

Spike, a RISC-V ISA Simulator
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for vl=0 does vfredsum need to make vd[0]=vs1[0]? #1673

Closed xinyuwang-starfive closed 4 months ago

xinyuwang-starfive commented 4 months ago

7b3f8f54fb214d2ad6338dd41e8c5a90 the spec say no element are active,the scalar in vs1[0] copied to vd[0]. if vl=0,does the vfredsum need to make vd[0]=vs1[0]

aswaterman commented 4 months ago

No, Spike is correct in this case. The highlighted text is describing the case that vstart < vl but no elements are unmasked. Also it's non-normative text. The general statement that "if vstart >= vl, no destination registers are written" is determinative.