zicflip: fix [ms]ret behavior

riscv-software-src / riscv-isa-sim

Spike, a RISC-V ISA Simulator

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zicflip: fix [ms]ret behavior #1675

Closed chihminchao closed 4 months ago

chihminchao commented 4 months ago

Based on spec chapter 3.5 "An MRET or SRET instruction is used to return from a trap in M-mode or S-mode, respectively. When executing an xRET instruction, if xPP holds the value y, then ELP is set to the value of xPELP if yLPE is 1; otherwise, it is set to NO_LP_EXPECTED; xPELP is set to NO_LP_EXPECTED."

The change follows the last statement after semicolon "xPELP is set to NO_LP_EXPECTED"

chihminchao commented 4 months ago

@mylai-mtk You may be interested at this.

mylai-mtk commented 4 months ago

I think you're right, but I don't have write access to the repo 😁