riscv-software-src / riscv-isa-sim

Spike, a RISC-V ISA Simulator
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vector: Not logging write of reduction instructions when vl = 0 #1677

Closed YenHaoChen closed 1 month ago

YenHaoChen commented 1 month ago

The spec says: "If vl=0, no operation is performed and the destination register is not updated." in Section 14. Vector Reduction Operations.

The commit proposes setting the variable is_write to false when vl = 0, which means not logging the write (instead of logging a write of the same value).