riscv-software-src / riscv-isa-sim

Spike, a RISC-V ISA Simulator
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vmv1r.v instruction's behavior #1680

Closed EventScheduler closed 1 month ago

EventScheduler commented 1 month ago

"vmv1r_v.h" will call "require_vector", which will check the "vill" bit. However, the spec says, "vset{i}vl{i} and whole-register loads, stores, and moves do not depend upon vtype." I think "vmv1r.v" is also a whole-register move instruction, so I don't think it should check the "vill" bit. so do vmv[248]r.v instructions.

aswaterman commented 1 month ago

The non-normative note you mention was clarified last year to delete "moves": https://github.com/riscv/riscv-v-spec/pull/872/files

The normative text says that vmv1r does depend on SEW, and hence depends on vtype, so implicitly must depend on vtype.vill. And of course normative text takes precedence over non-normative text, hence changing the non-normative text in the PR I linked to.