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riscv-software-src / riscv-isa-sim

Spike, a RISC-V ISA Simulator
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Dynamic CSR read/write mask #1692

Closed ved-rivos closed 2 weeks ago

ved-rivos commented 3 weeks ago

Some CSR fields may be read-only zero if the extension providing them is disabled in the controlling *envcfg CSR. Presently CSR read/write masks seem to be built statically based on whether the extension is enabled. Looking for some suggestion on best way to add the dynamic masking.

aswaterman commented 2 weeks ago

It is true that masked_csr_t requires the mask be static, but you can instead inherit directly from csr_t and implement your own custom read-masking function. This way, the masking can be a function of other dynamic state. For an example, see epc_csr_t, which forms its read mask based upon IALIGN, which can change at runtime when the C extension is disabled.

ved-rivos commented 2 weeks ago

Thanks. I will follow that form for mstatus and sstatus.