Spike behaviour: vector register overlap

[UzairHumayun]

I have the following instruction:

core   0: 0x000000080000006c (0x0116f7d7) vsetvli a5, a3, e32, m2, tu, mu
core   0: 3 0x000000080000006c (0x0116f7d7) x15 0x000000000000000a c8_vstart 0x0000000000000000 c3104_vl 0x000000000000000a c3105_vtype 0x0000000000000011 c768_mstatus 0x8000000a00000600
: 
core   0: 0x0000000800000070 (0xb2010057) vnsrl.wv v0, v0, v2
core   0: 3 0x0000000800000070 (0xb2010057) c8_vstart 0x0000000000000000 e32 m2 l10 v 0 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 c768_mstatus 0x8000000a00000600
: 
core   0: 0x0000000800000074 (0x0126f7d7) vsetvli a5, a3, e32, m4, tu, mu
core   0: 3 0x0000000800000074 (0x0126f7d7) x15 0x000000000000000a c8_vstart 0x0000000000000000 c3104_vl 0x000000000000000a c3105_vtype 0x0000000000000012 c768_mstatus 0x8000000a00000600
: 
core   0: 0x0000000800000078 (0xb2010057) vnsrl.wv v0, v0, v2
core   0: exception trap_illegal_instruction, epc 0x0000000800000078
core   0:           tval 0x00000000b2010057

As seen, spike throws an illegal exception when lmul = 4. Why is this so?

[aamartin0000]

When LMUL=4, "v0" of the instruction incudes {v3,v2,v1,v0}, so potentially v2 could be clobbered during the operation-- this is an illegal overlap, because the end result in {v3,v2,v1,v0} would be dependent on the order of operations. If you used v4 instead of v2, this would be legal.