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riscv-software-src / riscv-isa-sim

Spike, a RISC-V ISA Simulator
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Add Ssdbltrp #1700

Open ved-rivos opened 2 weeks ago

ved-rivos commented 2 weeks ago

Spec: https://github.com/riscv/riscv-double-trap Tests: https://github.com/riscv-non-isa/riscv-arch-test/pull/438

ved-rivos commented 2 weeks ago

This PR does not dynamically access control the SDT based on menvcfg.DTE - was hoping to get some guidance on that in issue #1692 . Next PR I would like to send is for Smdbltrp. For Smdbltrp I am requesting some guidance on a) for critical error what should be behavior - exit simulation? How best to do that b) Smrnmi does not model the RNMI delivery presently - it would require a command line switch to provided the NMI handler address - please suggest if this would be acceptable.

aswaterman commented 2 weeks ago

Sorry for the delay in responding to #1692. I guess it makes sense to wait to merge this PR until you've implemented menvcfg.DTE.

ved-rivos commented 1 day ago

@aswaterman thanks for the suggestion on dealing with menvcfg.DTE. I have made the updates.