riscv-software-src / riscv-isa-sim

Spike, a RISC-V ISA Simulator
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Bump encoding.h for dcsr in debug spec 1.0 #1719

Closed YenHaoChen closed 2 days ago

YenHaoChen commented 3 days ago

A recent riscv-opcodes commit revises dcsr fields to match 1.0 debug spec (https://github.com/riscv/riscv-opcodes/commit/a50bc1fea61536511032a34c93357aa34d27c46f). However, the update breaks Spike and results in compilation failure. This PR fixes the issue.

Rename DCSR_STOPCYCLE to DCSR_STOPCOUNT Rename DCSR_HALT to DCSR_NMIP