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riscv-software-src / riscv-isa-sim

Spike, a RISC-V ISA Simulator
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SPIKE functions use in System verilog #1743

Open svasekar opened 1 month ago

svasekar commented 1 month ago

I am trying to call sim_t function from spike.cc , in my cpp(c++) wrapper API (provided riscv-isa-sim build as input for compilation) to create shared object, which I will call in System verilog (SV) using DPI call. Idea is to use SPIKE source functions in SV testbench to get SPIKE results for an instruction as input. Will not cal SPIKE coammand in this flow. Alos loaded the elf file with linker script and program.S file (instruction input) to SPIKE and expecting SPIKE to execute its own flow/stack and then will call processor functions to get states, csr, registers in CPP file. however SPIKE stuck in mmu.cc flush_icache, I think i need to initialize ic, dc.
Question is this flow will work? I

jerryz123 commented 1 month ago

Using spike as a functional model for cosimulation via DPI works. Here is some example code demonstrating this use case. https://github.com/ucb-bar/testchipip/blob/master/src/main/resources/testchipip/csrc/cospike_impl.cc

svasekar commented 1 month ago

HI Jerryz123, Thanks a lot. While making an instance sim_t and calling run in cpp wrapper function, found that SPIKE stuck at function for icache. Not sure what could be the reason. In inital cfg-> ic/dc should we provide init values to it. Also I am not calling SPIKE as such , wanted to sue only functions.