Fetch access while writing to mtimecmp

[noureddine-as]

Hello, I'm trying to understand interrupts in RISC-V. Especially Machine Timer. Following the same fachion in coreboot and riscv-pk i could do that using SBI calls in Supervisor mode and handle them correctly.

However in M-mode, things were a little bit confusing. Inspired from riscv-tests, i tried to catch a simple Machine Timer interrupt, I display a message then (as I know) i set timecmp to (uint64_t)-1ULL to disable the timer as mentioned in a presentation of mr. Krste Asanovic. The thing is it fails there when I want to reconfigure the mtimecmp with a new value in the interrupt_handler, here are my test conclusions:

• In spike, I catch machine timer interrupt, but when I write to mtimecmp I get Cause = 1 : fetch access exception and it stops.

• In C++ Emulator (from verilator), I catch machine timer interrupt, but when I write to mtimecmp I get Cause = 2 : illegal instruction exception

I really would like to understand if there are any fundamental differences between these two environments when we talk about interrupts? Why does it fail when I set the mtimecmp inside the interrupt handler (it doesn't fail when I've configured it the first time before the interrupt)?

Concerning HW, I use Rocket-Chip with DefaultConfig

Best reagards!

[noureddine-as]

This was an instruction alignment issue, will close it now, sorry for that.

Best regards.