Closed jugonz closed 10 years ago
The 'install' target of riscv-opcodes was polluting the hwacha/opcodes_hwacha_ut.h
header with unimplemented instructions, as you might have observed with git-diff(1)
. Commit ucb-bar/riscv-opcodes@d4a26c50d1c8d69082533196b7f79e4762fb9637 sidesteps this; please pull the recent changes to riscv-tools and update the submodules.
Following the instructions on http://riscv.org/download.html#tab_isa-sim to simulate a new instruction, I always run into a build error:
make: *\ No rule to make target
insns_ut/ut_beq.h', needed by
ut_beq.cc`. Stop.I've installed riscv-isa-sim through the risc-v tools, have setup the prefix at $RISCV properly, I have not touched ut_beq and I followed step 3 by running ./build-spike-only.sh in riscv-tools.
Is there anything else I can add?