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riscv-software-src / riscv-isa-sim

Spike, a RISC-V ISA Simulator
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Disabling unimplemented processor modes User and Supervisor #336

Closed sdexter-numa closed 4 years ago

sdexter-numa commented 5 years ago

Is it possible in Spike to expect User and Supervisor modes to be disabled? This is an issue in my use case, because the Spike logger always expects certain bits of the mstatus CSR to be set, but they will never be set if the riscv processor dut is only in Machine Mode.

aswaterman commented 5 years ago

Not currently. You’ll need to hack the code to accomplish this.

On Thu, Sep 26, 2019 at 4:11 PM sdexter-numa notifications@github.com wrote:

Is it possible in Spike to expect User and Supervisor modes to be disabled? This is an issue in my use case, because the Spike logger always expects certain bits of the mstatus CSR to be set, but they will never be set if the riscv processor dut is only in Machine Mode.

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sdexter-numa commented 4 years ago

I was able to find a workaround. I'm using google's riscv-dv instruction generator, and it's possible within that to disable some bits in mstatus from ever being set, which means Spike won't take any issue with it.