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riscv-software-src / riscv-isa-sim

Spike, a RISC-V ISA Simulator
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Some instructions are not decoded as illegal instruction when running in rv32imc mode #418

Open Evgenii666 opened 4 years ago

Evgenii666 commented 4 years ago

I am running an illegal instruction test and expect that some instructions to be decoded as illegal instruction. However, spike decoded is as a vector instruction. This issue is similar to https://github.com/riscv/riscv-isa-sim/issues/313 and https://github.com/riscv/riscv-isa-sim/issues/325.

core 0: 0xffffffff80003a22 (0x0953f287) vlse.v v5, (t2), s5, v0.t core 0: 0xffffffff8000c646 (0x6ceaf207) vlxseg4e.v v4, (s5), v14, v0.t

aswaterman commented 4 years ago

@chihminchao

chihminchao commented 4 years ago

@Evgenii666 Do you use the HEAD version ?

Evgenii666 commented 4 years ago

At the time of writing the issues, I was using the latest version.

chihminchao commented 4 years ago

@Evgenii666 I can't reproduce it on my site with --isa=rv32imc and it trigger illegal exception.