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riscv-software-src / riscv-isa-sim

Spike, a RISC-V ISA Simulator
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CSR_*TIME not implemented #63

Open neuschaefer opened 8 years ago

neuschaefer commented 8 years ago

I noticed that, while CSR_TIME and CSR_STIME are redirected to CSR_MTIME, CSR_MTIME is not implemented, resulting in an "Illegal Instruction" exception everytime one of these CSRs is used. Although bbl seems to work around the lack of mtime somehow, it would be nice to have support for it in spike.

aswaterman commented 8 years ago

As with mtimecmp, we are leaning towards requiring the platform provide this register through its preferred means, rather than mandating it be a CSR.

The rationale is that the RTC necessarily lives in a different clock/power domain, and so is not part of the hart (hence CSR).

On Tuesday, August 23, 2016, neuschaefer notifications@github.com wrote:

I noticed that, while CSR_TIME and CSR_STIME are redirected https://github.com/riscv/riscv-isa-sim/blob/master/riscv/processor.cc#L425 to CSR_MTIME, CSR_MTIME is not implemented https://github.com/riscv/riscv-isa-sim/blob/master/riscv/processor.cc#L445, resulting in an "Illegal Instruction" exception everytime one of these CSRs is used. Although bbl seems to work around the lack of mtime somehow, it would be nice to have support for it in spike.

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neuschaefer commented 8 years ago

I guess the privileged spec 1.9 is outdated in this regard; it specifies: "M-mode includes a timer facility provided by the high-resolution read-only real-time counter mtime.", which does not sound optional.

Does spike use a memory-mapped RTC instead of mtime?

aswaterman commented 8 years ago

Yeah, we have rethought that decision. Sorry for being a pain in the ass :-/

On Tuesday, August 23, 2016, neuschaefer notifications@github.com wrote:

I guess the privileged spec 1.9 is outdated in this regard; it specifies: "M-mode includes a timer facility provided by the high-resolution read-only real-time counter mtime.", which does not sound optional.

Does spike use a memory-mapped RTC instead of mtime?

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colinschmidt commented 8 years ago

I just ran into this issue trying to get this commit of riscv-linux to boot. How should rdtime resolve itself in spike?

Its unclear to me whether the csr_time case should be re-added to the get_csr switch statment, or if the rdtime psuedo op needs to be updated to not use a csr? or something else entirely? for now I can pretty easily work around it but I was thinking about submitting a PR but I wasn't sure what the right solution was.