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riscv-software-src / riscv-isa-sim

Spike, a RISC-V ISA Simulator
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RV32I regs and mem shown as 64 bits #66

Open emelcher opened 8 years ago

emelcher commented 8 years ago

Using the following commands:

riscv64-unknown-elf-gcc -nostdlib -nostartfiles -Tlink.ld -m32 -o inst inst.s
spike --isa=RV32I -d inst

and then inside spike any of these:

pc 0
reg 0
mem 200

the values are displayed as 64 bit values (16 hex digits).

Is there a way to make spike simulate a 32 bit ISA with 32 bit pc, 32 bit registers and memory content displayed as 32 bit words?

aswaterman commented 8 years ago

We don't intend to fix this, but if you propose a patch and it doesn't touch too much code, we'll consider merging it.

ghost commented 6 years ago

possible link with https://github.com/riscv/riscv-isa-sim/issues/201