riscv-software-src / riscv-perf-model

Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
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Jeffnye.dromajo stf update #105

Closed jeffnye-gh closed 11 months ago

jeffnye-gh commented 11 months ago

This branch uses latest dromajo f3c3112, the changes move stf start/stop macro detection and trace generation into include/dromajo_template.h, within glue(riscv_cpu_interp, XLEN)(RISCVCPUState *s, int n_cycles)

I have done limited testing with dhrystone and coremark, single cpu, with zstf and stf. stf_diff reports no differences. (clarify: no differences between this and stf's generated by previous impl.)

The main loop body can exit w/ a goto, illegal_instructions/etc. The tracing code makes the assumption that exceptions are not traced. I'm looking at this more.

other minor changes:

klingaard commented 11 months ago

Hey @jeffnye-gh, do you think you can finish this PR up and mark it for review? This is good stuff.

jeffnye-gh commented 11 months ago

Hi Knute,

Previous implementation was not as clean as it looked.

I have an updated implementation on a branch in https://github.com/Condor-Performance-Modeling/dromajo, but I have not prepared a new PR.

The remaining problem is a stack pointer (x2) initialization difference at startup in dhrystone on linux. I need to figure out why.

Day job priorities got in the way, I'll be able to get back to this on the weekend.

jeff

ghost commented 11 months ago

No worries. Just wanted to make sure you weren't waiting on anything from our end.