riscv-software-src / riscv-perf-model

Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
Apache License 2.0
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Adding new sparta unit : L2Cache #109

Open Kunal-Buch opened 1 year ago

Kunal-Buch commented 1 year ago
ghost commented 1 year ago

An example of CycleCounter/stall counting: https://github.com/riscv-software-src/riscv-perf-model/blob/82504f6f68374d4b335d9de3d5d3890fe55e9838/core/Dispatch.hpp#L132

Presentation on Sparta, including example of how to handle multiple inputs and choose one output: https://docs.google.com/presentation/d/e/2PACX-1vS1BWtVv0x3qXKQWAeECe2gsF9cMG3Zp2HnXJw52grCAcl21lv3a9pLW6J0lZ32e5DWdZkFyUMcE_AI/pub?start=false&loop=false&delayms=3000

Move forward to "Ordered Scheduling"

Kunal-Buch commented 1 year ago

Thanks Knute! :)

I have updated the model for the backpressure handling when the buffers are full. I also have the make regress clean with the couple of tests added for the L2Cache.

Do I need permissions to create a remote branch and create a PR?

ghost commented 1 year ago

You can open a PR here that references your fork of Olympia. Once done, we will receive a note to enable CI and then we'll look it over. Thanks for contributing!

zhynsb commented 6 months ago

Hi, guys

Could you write a README to run tests with L1+L2 system?

Thanks :)