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riscv-software-src / riscv-perf-model

Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
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Handling flush in LSU updateIssuePriorityAfterCacheReload #136

Closed danbone closed 6 months ago

danbone commented 6 months ago

@h0lyalg0rithm

I'm trying to enable flushing and I'm hitting the assert in this code because the instruction was flushed.

https://github.com/riscv-software-src/riscv-perf-model/blob/e3e1412137f8b5ee647c223b31301538e4262039/core/LSU.cpp#L1178-L1196

Can I just return early if the instruction was flushed?

h0lyalg0rithm commented 6 months ago

@danbone Yes I think that can work. If spec_load is enabled we might need to either cancel those events or return early in the replay callback How are you flushing the instructions.

ullahnasr commented 6 months ago

The email knute.lingaard@sfive is no longer valid as Knute lingaard is not at Sifive anymore. He will update his emal address

klingaard commented 6 months ago

Thanks, Nasr. I updated the settings. You (in theory) shouldn't be receiving any more emails.

danbone commented 6 months ago

@h0lyalg0rithm see #137