Fix end of simulation empty buffer checks in LSU

riscv-software-src / riscv-perf-model

Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model

Apache License 2.0

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Fix end of simulation empty buffer checks in LSU #138

Closed danbone closed 6 months ago

danbone commented 6 months ago

I noticed that the buffer empty termination checks weren't working as intended.

danbone commented 6 months ago

Thanks, I don't have write access will you merge it? (not sure what the process is)

klingaard commented 6 months ago

Still new on the process. Currently those folks that are directly on this project can merge. Will need to do some chin-scratching with Arup to determine the "right of passage" for directly contributing. This is new to me...