riscv-software-src / riscv-perf-model

Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
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Use MemoryAccessInfo instead of Inst for passing requests between caches and MSS #144

Closed danbone closed 5 months ago

danbone commented 5 months ago

As part of #143 use MemoryAccessInfo as the standard transaction type for making memory requests outside of the core, instead of instructions.

This paves way for adding an instruction cache, as well as prefetching and more complicated memory subsystems where requests do not always correspond to a particularly instruction.

Changes are minor, mostly just renaming.