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riscv-software-src / riscv-perf-model

Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
Apache License 2.0
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Add an example of PEvent generation #145

Closed klingaard closed 5 months ago

klingaard commented 5 months ago

This SHA is an example of how to generate PEvents (Performance Events) typically used for correlation efforts between a perf model and hardware.

PEvents are a more "compact" form of the pipeout collection pairs, allowing a modeler to specify more direct items for collection. Pipeout pairs can be more elaborate/detailed. However, with some clever coding, there can be reuse -- it's not done here.

To generate performance events, use the command line parameter --pevents <filename> <pevent1,pevent2,...|all>.

Examples:

# All pevents
./olympia traces/dhry_riscv.zstf --pevents retire.out all -i100

# Just RETIRE pevent
./olympia traces/dhry_riscv.zstf --pevents retire.out RETIRE -i100

# RETIRE and COMPLETE pevent
./olympia traces/dhry_riscv.zstf --pevents retire.out COMPLETE,RETIRE -i100

While I was at it, I removed the generated annotation for pipeline collection for LoadStore/MemoryAccess classes -- uses NVP which generates faster, as well as creates smaller pipeouts.

klingaard commented 5 months ago

Looks good to me! You may also add a test for it.

Done! Zhen keeping me honest. :stuck_out_tongue: