Support Multiple pipelines in the LSU

riscv-software-src / riscv-perf-model

Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model

Apache License 2.0

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Support Multiple pipelines in the LSU #150

Open h0lyalg0rithm opened 5 months ago

h0lyalg0rithm commented 5 months ago

Add support for N load/store pipelines; this entails ensuring there are no collisions on the cache/mmu blocks between pipes (or add explicit support to allow that and assert when NOT requested)

h0lyalg0rithm commented 5 months ago

@klingaard I would like to work on this feature.If there is something that you think I should consider before implementing this please let me know