riscv-software-src / riscv-perf-model

Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
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Sparta Assert for Target Pipe without Execution Unit #151

Closed AaronGChan closed 5 months ago

AaronGChan commented 5 months ago

Forgot to add an assert to check that there is a dispatcher (thus a subsequent issue queue/execution unit) that can handle a target pipe of an instruction. If one forgets to define one, i.e you forget to define an execution unit to handle DIV target pipe, the simulator will end early, but no error will be thrown.