Add L1 Instruction Cache

riscv-software-src / riscv-perf-model

Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model

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Add L1 Instruction Cache #152

Open danbone opened 5 months ago

danbone commented 5 months ago

Adding an L1 Instruction Cache for fetch as noted in #143

Updated fetch unit so that it requests a block of instructions per cycle from the instruction cache. The block is formed based on the instruction's program counters.
Tidied up some coding style within the L2Cache/MSS.
Added tests for new instruction cache unit.
Changed MSS credit interfaces to be more like those used within the core.

danbone commented 5 months ago

I haven't managed to make much progress this week, rather than leave the PR to rot. I think I'd merge this and update #143 with the enhancements I'd hope to do, and open a new PR. Probably makes code review easier anyways.

arupc-vmicro commented 4 months ago

@danbone are you planning to add a documentation describing uarch of the modeled L1 Icache and changes to the fetch unit as a part of this PR?