Implement non blocking cache - Githubissues

riscv-software-src / riscv-perf-model

Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model

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Implement non blocking cache #157

Open h0lyalg0rithm opened 4 months ago

h0lyalg0rithm commented 4 months ago

Limitations of the Current Cache model:

It cannot handle multiple misses. It is a blocking cache.

Improvements to be made:

Design a non-blocking cache (Modelled similar to the E500 core)
Parameterizable Cache Hierarchy

Assumptions made:

There is only a single bank.
The cache line is not split into sub-blocks.
The memory transactions between the cache and the memory subsystem are of the same width as the cache line.
Olympia currently only supports a single core, so there is no implementation of cache coherence needed.
Cache is assumed to be non-inclusive.
Cache line size remains the same in all caches.