So, the existing implementation is functionally correct and operates as follows: All SYS instructions bypass the execution step and proceed directly to the ROB. When the instruction is retired, the ROB will flush. If there is a destination register, the ROB will remove it from the scoreboard.
Knute provided a more elegant solution, as follows: Every SYS instruction will go through an execution pipe, most likely the ALU pipe. This execution pipe will remove the destination register from the scoreboard after the instruction is executed. The execution unit will also determine whether retiring the instruction by the ROB will result in a flush. To facilitate this, we need to add a new flag to the INST structure.
I believe that the execution pipe, rather than the ROB, is the appropriate place to decide whether to flush because the decision is not straightforward. There are three native CSR instruction types, all of which are really atomic read-modify-write operations. However, two of the three categories are read-and-set and read-and-clear. When the set or clear bit register is x0, these two instructions become read-only. The modeling code to accomplish this will need to open up some data structures, which I believe are best suited for the execution pipe.
So, the existing implementation is functionally correct and operates as follows: All SYS instructions bypass the execution step and proceed directly to the ROB. When the instruction is retired, the ROB will flush. If there is a destination register, the ROB will remove it from the scoreboard.
Knute provided a more elegant solution, as follows: Every SYS instruction will go through an execution pipe, most likely the ALU pipe. This execution pipe will remove the destination register from the scoreboard after the instruction is executed. The execution unit will also determine whether retiring the instruction by the ROB will result in a flush. To facilitate this, we need to add a new flag to the INST structure.
I believe that the execution pipe, rather than the ROB, is the appropriate place to decide whether to flush because the decision is not straightforward. There are three native CSR instruction types, all of which are really atomic read-modify-write operations. However, two of the three categories are read-and-set and read-and-clear. When the set or clear bit register is x0, these two instructions become read-only. The modeling code to accomplish this will need to open up some data structures, which I believe are best suited for the execution pipe.
Please give me your thoughts or comments.