riscv-software-src / riscv-perf-model

Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
Apache License 2.0
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Non blocking cache implementation #166

Open h0lyalg0rithm opened 3 months ago

h0lyalg0rithm commented 3 months ago

The implementation is based on the previous work by Vineeth. However I made change to use a single pipeline and reduce the number of events generated inside the Dache. I has also removed the col-easing of the mshr requests (based on the block address) instead each request generates an mshr and the same instruction is then sent to next cache for lookup in case of a miss.

Micro architecture details https://docs.google.com/document/d/1HLlCkfZUtt6BafgVypS5pwS90zo4XOrGFOR1KIzYHLw/edit?usp=sharing