It is also discussed in: https://github.com/riscv-software-src/riscv-perf-model/issues/164
This PR changes the way SYS instructions are executed. Previously, SYS instructions did not go through an execution pipe but instead were dispatched to the ROB without delay, and the ROB handled the scoreboard with respect to the destination register. This PR requires the SYS instructions to pass through an execution pipe, thereby obviating any special scoreboard code in the ROB. With the exception of CSR read instructions, the ROB will flush all SYS instructions.
This feature can be tested by running example_json.json workload, which is part of the make regress suite. Also, the sys execute pipe was added to 3 config files big_core, medium_core and small_core.
This PR is a followup to https://github.com/riscv-software-src/riscv-perf-model/pull/162.
It is also discussed in: https://github.com/riscv-software-src/riscv-perf-model/issues/164 This PR changes the way SYS instructions are executed. Previously, SYS instructions did not go through an execution pipe but instead were dispatched to the ROB without delay, and the ROB handled the scoreboard with respect to the destination register. This PR requires the SYS instructions to pass through an execution pipe, thereby obviating any special scoreboard code in the ROB. With the exception of CSR read instructions, the ROB will flush all SYS instructions.
This feature can be tested by running example_json.json workload, which is part of the make regress suite. Also, the sys execute pipe was added to 3 config files big_core, medium_core and small_core.
How was this tested: make regress passes 83/83.