Generate traces for open source vector workloads

riscv-software-src / riscv-perf-model

Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model

Apache License 2.0

117 stars 43 forks source link

Open arupc opened 1 month ago

arupc commented 1 month ago

AaronGChan commented 1 month ago

https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/main/examples has some examples of using RISCV vector intrinsics that could be used to generate simple vector traces.