Closed nickisobrien closed 4 years ago
While it's unused upstream, according to the SiFive FU540 document, the UART divisor register is at offset 0x18.
This also maps the interrupt enable and interrupt pending register offsets.
While it's unused upstream, according to the SiFive FU540 document, the UART divisor register is at offset 0x18.
This also maps the interrupt enable and interrupt pending register offsets.