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riscv-software-src / riscv-pk

RISC-V Proxy Kernel
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Set desired endianness at boot time #247

Closed zeldin closed 3 years ago

aswaterman commented 3 years ago

This is a regression. Most RV32 cores don’t have the mstatush register, and so this will break them.

zeldin commented 3 years ago

Hm, so how do you find out whether or not the register exists? Is the only way trying to access it and handle the trap?

zeldin commented 3 years ago

Is it ok to assume mstatush exists if pk is compiled as big endian? I'm guessing all those cores which lack mstatush are little-endian only... It's really only in that case where mstatush strictly needs to be written; if the core has configurable endianness it's supposed to go LE on reset, and if it's big endian only then writing mstatush will not do anything even if it exists... Or maybe the problem then would be SBE (if it exists), since only MBE is required to be cleared on reset IIRC.

aswaterman commented 3 years ago

Yes, @zeldin, I agree that’s a safe assumption, since the feature didn’t exist until the mstatush CSR also existed.

zeldin commented 3 years ago

I updated the code to only write mstatush when __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__. I also removed the clear of MBE on RV64 little endian, for consistency.

aswaterman commented 3 years ago

This version looks good to me; thanks, @zeldin.