According to the vector extension, if the XLEN<SEW, then the value from the X register is sign-extended to SEW bits.
When the element width is 64, but XLEN is just 32. That means whether it is a signed algorithm or unsigned algorithm, the rs1 from GPR should be sign-extended to 64 bits according to the highest bit of rs1. But in spike it doesn’t show the rs1 is sign-extened.
For example, If rs1=0xc0cc_d0dd, then the 64 bits operator after sign-extended is 0xffff_ffff_c0cc_d0dd.
But when I check the spike, I cannot see any sign-extended logic there.
According to the vector extension, if the XLEN<SEW, then the value from the X register is sign-extended to SEW bits. When the element width is 64, but XLEN is just 32. That means whether it is a signed algorithm or unsigned algorithm, the rs1 from GPR should be sign-extended to 64 bits according to the highest bit of rs1. But in spike it doesn’t show the rs1 is sign-extened. For example, If rs1=0xc0cc_d0dd, then the 64 bits operator after sign-extended is 0xffff_ffff_c0cc_d0dd. But when I check the spike, I cannot see any sign-extended logic there.