search

riscv-software-src / riscv-tests

Other
894 stars 462 forks source link

How to compile the test code dot S #168

Open mongsim opened 6 years ago

mongsim commented 6 years ago

Can anyone show an example of how to compile the tests code .s files with riscv64-unknown-elf-gcc.

tovine commented 6 years ago

Could you be a bit more specific about which .S files? Usually one just compiles and runs a specific test by navigating to the directory with the Makefile (like this one: https://github.com/riscv/riscv-tests/blob/master/isa/Makefile) and runs make from there...

mongsim commented 6 years ago

Hello Torbjorn,

Thank you for your fast reply!

I tried this simple command line compilation and got these errors. Any help is greatly appreciated.

riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles add.s -o add.o

add.s: Assembler messages: add.s:13: Error: unrecognized opcode rvtest_rv32u' add.s:14: Error: unrecognized opcodervtest_code_begin' add.s:20: Error: unrecognized opcode test_rr_op( 2,add,0x00000000,0x00000000,0x00000000)' add.s:21: Error: unrecognized opcodetest_rr_op( 3,add,0x00000002,0x00000001,0x00000001)' add.s:22: Error: unrecognized opcode test_rr_op( 4,add,0x0000000a,0x00000003,0x00000007)' add.s:24: Error: unrecognized opcodetest_rr_op( 5,add,0xffff8000,0x00000000,0xffff8000)' add.s:25: Error: unrecognized opcode test_rr_op( 6,add,0x80000000,0x80000000,0x00000000)' add.s:26: Error: unrecognized opcodetest_rr_op( 7,add,0x7fff8000,0x80000000,0xffff8000)' add.s:28: Error: unrecognized opcode test_rr_op( 8,add,0x00007fff,0x00000000,0x00007fff)' add.s:29: Error: unrecognized opcodetest_rr_op( 9,add,0x7fffffff,0x7fffffff,0x00000000)' add.s:30: Error: unrecognized opcode `test_rr_op( 10,add,0x80007ffe,0x7fffffff,0x00007fff)'

Thank you,

Mong

Sent from Mailhttps://go.microsoft.com/fwlink/?LinkId=550986 for Windows 10

From: Torbjørn notifications@github.com Sent: Tuesday, October 23, 2018 9:42:40 AM To: riscv/riscv-tests Cc: mongsim; Author Subject: Re: [riscv/riscv-tests] How to compile the test code dot S (#168)

Could you be a bit more specific about which .S files? Usually one just compiles and runs a specific test by navigating to the directory with the Makefile (like this one: https://github.com/riscv/riscv-tests/blob/master/isa/Makefile) and runs make from there...

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHubhttps://github.com/riscv/riscv-tests/issues/168#issuecomment-432297522, or mute the threadhttps://github.com/notifications/unsubscribe-auth/AFbuSKZmdhTmmVOhM9dwds6P6IAn5mlRks5unzjwgaJpZM4XzyEb.

ifndef _ENV_PICORV32_TEST_H

define _ENV_PICORV32_TEST_H

ifndef TEST_FUNC_NAME

define TEST_FUNC_NAME mytest

define TEST_FUNC_TXT "mytest"

define TEST_FUNC_RET mytest_ret

endif

define RVTEST_RV32U

define TESTNUM x28

define RVTEST_CODE_BEGIN \

.text;              \
.global TEST_FUNC_NAME;     \
.global TEST_FUNC_RET;      \

TEST_FUNC_NAME: \ lui a0,%hi(.test_name); \ addi a0,a0,%lo(.test_name); \ lui a2,0x10000000>>12; \ .prname_next: \ lb a1,0(a0); \ beq a1,zero,.prname_done; \ sw a1,0(a2); \ addi a0,a0,1; \ jal zero,.prname_next; \ .test_name: \ .ascii TEST_FUNC_TXT; \ .byte 0x00; \ .balign 4, 0; \ .prname_done: \ addi a1,zero,'.'; \ sw a1,0(a2); \ sw a1,0(a2);

define RVTEST_PASS \

lui a0,0x10000000>>12;  \
addi    a1,zero,'O';        \
addi    a2,zero,'K';        \
addi    a3,zero,'\n';       \
sw  a1,0(a0);       \
sw  a2,0(a0);       \
sw  a3,0(a0);       \
jal zero,TEST_FUNC_RET;

define RVTEST_FAIL \

lui a0,0x10000000>>12;  \
addi    a1,zero,'E';        \
addi    a2,zero,'R';        \
addi    a3,zero,'O';        \
addi    a4,zero,'\n';       \
sw  a1,0(a0);       \
sw  a2,0(a0);       \
sw  a2,0(a0);       \
sw  a3,0(a0);       \
sw  a2,0(a0);       \
sw  a4,0(a0);       \
ebreak;

define RVTEST_CODE_END

define RVTEST_DATA_BEGIN .balign 4;

define RVTEST_DATA_END

endif

// See LICENSE for license details.

ifndef __TEST_MACROS_SCALAR_H

define __TEST_MACROS_SCALAR_H

-----------------------------------------------------------------------

Helper macros

-----------------------------------------------------------------------

define TEST_CASE( testnum, testreg, correctval, code... ) \

test_ ## testnum: \ code; \ li x29, correctval; \ li TESTNUM, testnum; \ bne testreg, x29, fail;

We use a macro hack to simpify code generation for various numbers

of bubble cycles.

define TEST_INSERT_NOPS_0

define TEST_INSERT_NOPS_1 nop; TEST_INSERT_NOPS_0

define TEST_INSERT_NOPS_2 nop; TEST_INSERT_NOPS_1

define TEST_INSERT_NOPS_3 nop; TEST_INSERT_NOPS_2

define TEST_INSERT_NOPS_4 nop; TEST_INSERT_NOPS_3

define TEST_INSERT_NOPS_5 nop; TEST_INSERT_NOPS_4

define TEST_INSERT_NOPS_6 nop; TEST_INSERT_NOPS_5

define TEST_INSERT_NOPS_7 nop; TEST_INSERT_NOPS_6

define TEST_INSERT_NOPS_8 nop; TEST_INSERT_NOPS_7

define TEST_INSERT_NOPS_9 nop; TEST_INSERT_NOPS_8

define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9

-----------------------------------------------------------------------

RV64UI MACROS

-----------------------------------------------------------------------

-----------------------------------------------------------------------

Tests for instructions with immediate operand

-----------------------------------------------------------------------

define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))

define TEST_IMM_OP( testnum, inst, result, val1, imm ) \

TEST_CASE( testnum, x3, result, \
  li  x1, val1; \
  inst x3, x1, SEXT_IMM(imm); \
)

define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \

TEST_CASE( testnum, x1, result, \
  li  x1, val1; \
  inst x1, x1, SEXT_IMM(imm); \
)

define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \

TEST_CASE( testnum, x6, result, \
  li  x4, 0; \

1: li x1, val1; \ inst x3, x1, SEXT_IMM(imm); \ TEST_INSERTNOPS ## nop_cycles \ addi x6, x3, 0; \ addi x4, x4, 1; \ li x5, 2; \ bne x4, x5, 1b \ )

define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \

TEST_CASE( testnum, x3, result, \
  li  x4, 0; \

1: li x1, val1; \ TEST_INSERTNOPS ## nop_cycles \ inst x3, x1, SEXT_IMM(imm); \ addi x4, x4, 1; \ li x5, 2; \ bne x4, x5, 1b \ )

define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \

TEST_CASE( testnum, x1, result, \
  inst x1, x0, SEXT_IMM(imm); \
)

define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \

TEST_CASE( testnum, x0, 0, \
  li  x1, val1; \
  inst x0, x1, SEXT_IMM(imm); \
)

-----------------------------------------------------------------------

Tests for vector config instructions

-----------------------------------------------------------------------

define TEST_VSETCFGIVL( testnum, nxpr, nfpr, bank, vl, result ) \

TEST_CASE( testnum, x1, result, \
  li x1, (bank << 12); \
  vsetcfg x1,nxpr,nfpr; \
  li x1, vl; \
  vsetvl x1,x1; \
)

define TEST_VVCFG( testnum, nxpr, nfpr, bank, vl, result ) \

TEST_CASE( testnum, x1, result, \
  li x1, (bank << 12) | (nfpr << 6) | nxpr; \
  vsetcfg x1; \
  li x1, vl; \
  vsetvl x1,x1; \
)

define TEST_VSETVL( testnum, nxpr, nfpr, bank, vl, result ) \

TEST_CASE( testnum, x1, result, \
  li x1, (bank << 12); \
  vsetcfg x1,nxpr,nfpr; \
  li x1, vl; \
  vsetvl x1, x1; \
)

-----------------------------------------------------------------------

Tests for an instruction with register operands

-----------------------------------------------------------------------

define TEST_R_OP( testnum, inst, result, val1 ) \

TEST_CASE( testnum, x3, result, \
  li  x1, val1; \
  inst x3, x1; \
)

define TEST_R_SRC1_EQ_DEST( testnum, inst, result, val1 ) \

TEST_CASE( testnum, x1, result, \
  li  x1, val1; \
  inst x1, x1; \
)

define TEST_R_DEST_BYPASS( testnum, nop_cycles, inst, result, val1 ) \

TEST_CASE( testnum, x6, result, \
  li  x4, 0; \

1: li x1, val1; \ inst x3, x1; \ TEST_INSERTNOPS ## nop_cycles \ addi x6, x3, 0; \ addi x4, x4, 1; \ li x5, 2; \ bne x4, x5, 1b \ )

-----------------------------------------------------------------------

Tests for an instruction with register-register operands

-----------------------------------------------------------------------

define TEST_RR_OP( testnum, inst, result, val1, val2 ) \

TEST_CASE( testnum, x3, result, \
  li  x1, val1; \
  li  x2, val2; \
  inst x3, x1, x2; \
)

define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \

TEST_CASE( testnum, x1, result, \
  li  x1, val1; \
  li  x2, val2; \
  inst x1, x1, x2; \
)

define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \

TEST_CASE( testnum, x2, result, \
  li  x1, val1; \
  li  x2, val2; \
  inst x2, x1, x2; \
)

define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \

TEST_CASE( testnum, x1, result, \
  li  x1, val1; \
  inst x1, x1, x1; \
)

define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \

TEST_CASE( testnum, x6, result, \
  li  x4, 0; \

1: li x1, val1; \ li x2, val2; \ inst x3, x1, x2; \ TEST_INSERTNOPS ## nop_cycles \ addi x6, x3, 0; \ addi x4, x4, 1; \ li x5, 2; \ bne x4, x5, 1b \ )

define TEST_RR_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \

TEST_CASE( testnum, x3, result, \
  li  x4, 0; \

1: li x1, val1; \ TEST_INSERTNOPS ## src1_nops \ li x2, val2; \ TEST_INSERTNOPS ## src2_nops \ inst x3, x1, x2; \ addi x4, x4, 1; \ li x5, 2; \ bne x4, x5, 1b \ )

define TEST_RR_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \

TEST_CASE( testnum, x3, result, \
  li  x4, 0; \

1: li x2, val2; \ TEST_INSERTNOPS ## src1_nops \ li x1, val1; \ TEST_INSERTNOPS ## src2_nops \ inst x3, x1, x2; \ addi x4, x4, 1; \ li x5, 2; \ bne x4, x5, 1b \ )

define TEST_RR_ZEROSRC1( testnum, inst, result, val ) \

TEST_CASE( testnum, x2, result, \
  li x1, val; \
  inst x2, x0, x1; \
)

define TEST_RR_ZEROSRC2( testnum, inst, result, val ) \

TEST_CASE( testnum, x2, result, \
  li x1, val; \
  inst x2, x1, x0; \
)

define TEST_RR_ZEROSRC12( testnum, inst, result ) \

TEST_CASE( testnum, x1, result, \
  inst x1, x0, x0; \
)

define TEST_RR_ZERODEST( testnum, inst, val1, val2 ) \

TEST_CASE( testnum, x0, 0, \
  li x1, val1; \
  li x2, val2; \
  inst x0, x1, x2; \
)

-----------------------------------------------------------------------

Test memory instructions

-----------------------------------------------------------------------

define TEST_LD_OP( testnum, inst, result, offset, base ) \

TEST_CASE( testnum, x3, result, \
  la  x1, base; \
  inst x3, offset(x1); \
)

define TEST_ST_OP( testnum, load_inst, store_inst, result, offset, base ) \

TEST_CASE( testnum, x3, result, \
  la  x1, base; \
  li  x2, result; \
  store_inst x2, offset(x1); \
  load_inst x3, offset(x1); \
)

define TEST_LD_DEST_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \

test_ ## testnum: \ li TESTNUM, testnum; \ li x4, 0; \ 1: la x1, base; \ inst x3, offset(x1); \ TEST_INSERTNOPS ## nop_cycles \ addi x6, x3, 0; \ li x29, result; \ bne x6, x29, fail; \ addi x4, x4, 1; \ li x5, 2; \ bne x4, x5, 1b; \

define TEST_LD_SRC1_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \

test_ ## testnum: \ li TESTNUM, testnum; \ li x4, 0; \ 1: la x1, base; \ TEST_INSERTNOPS ## nop_cycles \ inst x3, offset(x1); \ li x29, result; \ bne x3, x29, fail; \ addi x4, x4, 1; \ li x5, 2; \ bne x4, x5, 1b \

define TEST_ST_SRC12_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \

test_ ## testnum: \ li TESTNUM, testnum; \ li x4, 0; \ 1: li x1, result; \ TEST_INSERTNOPS ## src1_nops \ la x2, base; \ TEST_INSERTNOPS ## src2_nops \ store_inst x1, offset(x2); \ load_inst x3, offset(x2); \ li x29, result; \ bne x3, x29, fail; \ addi x4, x4, 1; \ li x5, 2; \ bne x4, x5, 1b \

define TEST_ST_SRC21_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \

test_ ## testnum: \ li TESTNUM, testnum; \ li x4, 0; \ 1: la x2, base; \ TEST_INSERTNOPS ## src1_nops \ li x1, result; \ TEST_INSERTNOPS ## src2_nops \ store_inst x1, offset(x2); \ load_inst x3, offset(x2); \ li x29, result; \ bne x3, x29, fail; \ addi x4, x4, 1; \ li x5, 2; \ bne x4, x5, 1b \

-----------------------------------------------------------------------

Test branch instructions

-----------------------------------------------------------------------

define TEST_BR1_OP_TAKEN( testnum, inst, val1 ) \

test_ ## testnum: \ li TESTNUM, testnum; \ li x1, val1; \ inst x1, 2f; \ bne x0, TESTNUM, fail; \ 1: bne x0, TESTNUM, 3f; \ 2: inst x1, 1b; \ bne x0, TESTNUM, fail; \ 3:

define TEST_BR1_OP_NOTTAKEN( testnum, inst, val1 ) \

test_ ## testnum: \ li TESTNUM, testnum; \ li x1, val1; \ inst x1, 1f; \ bne x0, TESTNUM, 2f; \ 1: bne x0, TESTNUM, fail; \ 2: inst x1, 1b; \ 3:

define TEST_BR1_SRC1_BYPASS( testnum, nop_cycles, inst, val1 ) \

test_ ## testnum: \ li TESTNUM, testnum; \ li x4, 0; \ 1: li x1, val1; \ TEST_INSERTNOPS ## nop_cycles \ inst x1, fail; \ addi x4, x4, 1; \ li x5, 2; \ bne x4, x5, 1b \

define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2 ) \

test_ ## testnum: \ li TESTNUM, testnum; \ li x1, val1; \ li x2, val2; \ inst x1, x2, 2f; \ bne x0, TESTNUM, fail; \ 1: bne x0, TESTNUM, 3f; \ 2: inst x1, x2, 1b; \ bne x0, TESTNUM, fail; \ 3:

define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \

test_ ## testnum: \ li TESTNUM, testnum; \ li x1, val1; \ li x2, val2; \ inst x1, x2, 1f; \ bne x0, TESTNUM, 2f; \ 1: bne x0, TESTNUM, fail; \ 2: inst x1, x2, 1b; \ 3:

define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \

test_ ## testnum: \ li TESTNUM, testnum; \ li x4, 0; \ 1: li x1, val1; \ TEST_INSERTNOPS ## src1_nops \ li x2, val2; \ TEST_INSERTNOPS ## src2_nops \ inst x1, x2, fail; \ addi x4, x4, 1; \ li x5, 2; \ bne x4, x5, 1b \

define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \

test_ ## testnum: \ li TESTNUM, testnum; \ li x4, 0; \ 1: li x2, val2; \ TEST_INSERTNOPS ## src1_nops \ li x1, val1; \ TEST_INSERTNOPS ## src2_nops \ inst x1, x2, fail; \ addi x4, x4, 1; \ li x5, 2; \ bne x4, x5, 1b \

-----------------------------------------------------------------------

Test jump instructions

-----------------------------------------------------------------------

define TEST_JR_SRC1_BYPASS( testnum, nop_cycles, inst ) \

test_ ## testnum: \ li TESTNUM, testnum; \ li x4, 0; \ 1: la x6, 2f; \ TEST_INSERTNOPS ## nop_cycles \ inst x6; \ bne x0, TESTNUM, fail; \ 2: addi x4, x4, 1; \ li x5, 2; \ bne x4, x5, 1b \

define TEST_JALR_SRC1_BYPASS( testnum, nop_cycles, inst ) \

test_ ## testnum: \ li TESTNUM, testnum; \ li x4, 0; \ 1: la x6, 2f; \ TEST_INSERTNOPS ## nop_cycles \ inst x19, x6, 0; \ bne x0, TESTNUM, fail; \ 2: addi x4, x4, 1; \ li x5, 2; \ bne x4, x5, 1b \

-----------------------------------------------------------------------

RV64UF MACROS

-----------------------------------------------------------------------

-----------------------------------------------------------------------

Tests floating-point instructions

-----------------------------------------------------------------------

define TEST_FP_OP_S_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \

test ## testnum: \ li TESTNUM, testnum; \ la a0, test ## testnum ## data ;\ flw f0, 0(a0); \ flw f1, 4(a0); \ flw f2, 8(a0); \ lw a3, 12(a0); \ code; \ fsflags a1, x0; \ li a2, flags; \ bne a0, a3, fail; \ bne a1, a2, fail; \ j 2f; \ .align 2; \ .data; \ test ## testnum ## _data: \ .float val1; \ .float val2; \ .float val3; \ .result; \ .text; \ 2:

define TEST_FP_OP_D_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \

test ## testnum: \ li TESTNUM, testnum; \ la a0, test ## testnum ## data ;\ fld f0, 0(a0); \ fld f1, 8(a0); \ fld f2, 16(a0); \ ld a3, 24(a0); \ code; \ fsflags a1, x0; \ li a2, flags; \ bne a0, a3, fail; \ bne a1, a2, fail; \ j 2f; \ .data; \ .align 3; \ test ## testnum ## _data: \ .double val1; \ .double val2; \ .double val3; \ .result; \ .text; \ 2:

define TEST_FCVT_S_D( testnum, result, val1 ) \

TEST_FP_OP_D_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \ fcvt.s.d f3, f0; fcvt.d.s f3, f3; fmv.x.d a0, f3)

define TEST_FCVT_D_S( testnum, result, val1 ) \

TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \ fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3)

define TEST_FP_OP1_S( testnum, inst, flags, result, val1 ) \

TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, 0.0, 0.0, \ inst f3, f0; fmv.x.s a0, f3)

define TEST_FP_OP1_D( testnum, inst, flags, result, val1 ) \

TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \ inst f3, f0; fmv.x.d a0, f3)

define TEST_FP_OP2_S( testnum, inst, flags, result, val1, val2 ) \

TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, 0.0, \ inst f3, f0, f1; fmv.x.s a0, f3)

define TEST_FP_OP2_D( testnum, inst, flags, result, val1, val2 ) \

TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \ inst f3, f0, f1; fmv.x.d a0, f3)

define TEST_FP_OP3_S( testnum, inst, flags, result, val1, val2, val3 ) \

TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, val3, \ inst f3, f0, f1, f2; fmv.x.s a0, f3)

define TEST_FP_OP3_D( testnum, inst, flags, result, val1, val2, val3 ) \

TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, val3, \ inst f3, f0, f1, f2; fmv.x.d a0, f3)

define TEST_FP_INT_OP_S( testnum, inst, flags, result, val1, rm ) \

TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \ inst a0, f0, rm)

define TEST_FP_INT_OP_D( testnum, inst, flags, result, val1, rm ) \

TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ inst a0, f0, rm)

define TEST_FP_CMP_OP_S( testnum, inst, result, val1, val2 ) \

TEST_FP_OP_S_INTERNAL( testnum, 0, word result, val1, val2, 0.0, \ inst a0, f0, f1)

define TEST_FP_CMP_OP_D( testnum, inst, result, val1, val2 ) \

TEST_FP_OP_D_INTERNAL( testnum, 0, dword result, val1, val2, 0.0, \ inst a0, f0, f1)

define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \

test ## testnum: \ li TESTNUM, testnum; \ la a0, test ## testnum ## data ;\ lw a3, 0(a0); \ li a0, val1; \ inst f0, a0; \ fsflags x0; \ fmv.x.s a0, f0; \ bne a0, a3, fail; \ j 1f; \ .align 2; \ test ## testnum ## _data: \ .float result; \ 1:

define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \

test ## testnum: \ li TESTNUM, testnum; \ la a0, test ## testnum ## data ;\ ld a3, 0(a0); \ li a0, val1; \ inst f0, a0; \ fsflags x0; \ fmv.x.d a0, f0; \ bne a0, a3, fail; \ j 1f; \ .align 3; \ test ## testnum ## _data: \ .double result; \ 1:

-----------------------------------------------------------------------

Pass and fail code (assumes test num is in TESTNUM)

-----------------------------------------------------------------------

define TEST_PASSFAIL \

    bne x0, TESTNUM, pass; \

fail: \ RVTEST_FAIL; \ pass: \ RVTEST_PASS \

-----------------------------------------------------------------------

Test data section

-----------------------------------------------------------------------

define TEST_DATA

endif

tovine commented 6 years ago

That looks a bit strange, when I run make (from the riscv-tests/isa dir) this is what comes out:

riscv32-unknown-elf-gcc -march=rv32g -mabi=ilp32 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I./../env/p -I./macros/scalar -T./../env/p/link.ld rv32mi/shamt.S -o rv32mi-p-shamt
riscv32-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data rv32mi-p-shamt > rv32mi-p-shamt.dump

It seems like what you're missing is I./../env/p -I./macros/scalar -T./../env/p/link.ld (update relative paths to match your working directory) because the test_rr_op is a preprocessor macro defined in riscv-tests/isa/macros/scalar/test_macros.h

mongsim commented 6 years ago

Thank you Torbjorn, I got it working.

Sent from Mailhttps://go.microsoft.com/fwlink/?LinkId=550986 for Windows 10

From: Torbjørn notifications@github.com Sent: Monday, November 5, 2018 8:26:45 AM To: riscv/riscv-tests Cc: mongsim; Author Subject: Re: [riscv/riscv-tests] How to compile the test code dot S (#168)

That looks a bit strange, when I run make (from the riscv-tests/isa dir) this is what comes out:

riscv32-unknown-elf-gcc -march=rv32g -mabi=ilp32 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I./../env/p -I./macros/scalar -T./../env/p/link.ld rv32mi/shamt.S -o rv32mi-p-shamt riscv32-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data rv32mi-p-shamt > rv32mi-p-shamt.dump

It seems like what you're missing is I./../env/p -I./macros/scalar -T./../env/p/link.ld (update relative paths to match your working directory) because the test_rr_op is a preprocessor macro defined in riscv-tests/isa/macros/scalar/test_macros.h

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHubhttps://github.com/riscv/riscv-tests/issues/168#issuecomment-435915624, or mute the threadhttps://github.com/notifications/unsubscribe-auth/AFbuSDtDHFmvLfMzpIcip2NmPTo_Osx1ks5usFi1gaJpZM4XzyEb.

tovine commented 6 years ago

Glad I could help! 😄

mongsim commented 5 years ago

Hello Torbjorn,

I have two questions hope you can help 😊 and Happy Thanksgiving!

  1. Do you have a coremark port that I can use? The trend is towards coremark.
  2. I an using a 32-bit data memory and would like to take advantage of the data bus width and also to implement later a icache too. Do you have a good solution to handle the 16bit compression and the regular 32-bit instructions?

Thank you,

Mong

Sent from Mailhttps://go.microsoft.com/fwlink/?LinkId=550986 for Windows 10

From: Torbjørn notifications@github.com Sent: Thursday, November 8, 2018 2:02:25 AM To: riscv/riscv-tests Cc: mongsim; Author Subject: Re: [riscv/riscv-tests] How to compile the test code dot S (#168)

Glad I could help! 😄

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHubhttps://github.com/riscv/riscv-tests/issues/168#issuecomment-436921500, or mute the threadhttps://github.com/notifications/unsubscribe-auth/AFbuSMZw0p50Zkl5stSQcKtW3nLAwUNNks5us_MhgaJpZM4XzyEb.

tovine commented 5 years ago
  1. Do you have a coremark port that I can use? The trend is towards coremark.

Unfortunately I don't, but it's pretty straightforward to port it - you just have to implement the relevant functions that are missing in this file: https://github.com/eembc/coremark/blob/master/barebones/core_portme.c

  1. I an using a 32-bit data memory and would like to take advantage of the data bus width and also to implement later a icache too. Do you have a good solution to handle the 16bit compression and the regular 32-bit instructions?

I'm sorry, no, I don't have enough experience with that yet.
However, you can take a look at the RISC-V HW Dev mailing list archives here to see if you can find something useful, or send a question to the list if it hasn't been discussed before: https://groups.google.com/a/groups.riscv.org/forum/#!forum/hw-dev

Good luck with your project!

mongsim commented 5 years ago

Hello Torbjon,

I was able to continue and is successful with both Dhrystones and Coremark without the compressed instruction or the “c” compiler option. When using the compile option, the processor passed the Test Suite except two test cases, Jal and Jalr. Is there anything special about this two instructions that is difference from the 32-bit version beside having PC + 2 instead of PC + 4.

Is there a need to modify these two tests (I believe many people have used this test suite) ?

Any help is greatly appreciated 😊

Thank you,

Mong

Sent from Mailhttps://go.microsoft.com/fwlink/?LinkId=550986 for Windows 10

From: Torbjørn notifications@github.com Sent: Friday, November 23, 2018 3:20:21 AM To: riscv/riscv-tests Cc: mongsim; Author Subject: Re: [riscv/riscv-tests] How to compile the test code dot S (#168)

  1. Do you have a coremark port that I can use? The trend is towards coremark.

Unfortunately I don't, but it's pretty straightforward to port it - you just have to implement the relevant functions that are missing in this file: https://github.com/eembc/coremark/blob/master/barebones/core_portme.c

  1. I an using a 32-bit data memory and would like to take advantage of the data bus width and also to implement later a icache too. Do you have a good solution to handle the 16bit compression and the regular 32-bit instructions?

I'm sorry, no, I don't have enough experience with that yet. However, you can take a look at the RISC-V HW Dev mailing list archives here to see if you can find something useful, or send a question to the list if it hasn't been discussed before: https://groups.google.com/a/groups.riscv.org/forum/#!forum/hw-dev

Good luck with your project!

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHubhttps://github.com/riscv/riscv-tests/issues/168#issuecomment-441202679, or mute the threadhttps://github.com/notifications/unsubscribe-auth/AFbuSI1eR27Fm6MLlC0AyLmQYZtemPBzks5ux8vlgaJpZM4XzyEb.

tovine commented 5 years ago

I don't know, sorry. Haven't really worked enough with the C extension to be familiar with it, then only thing I can recommend is to read the relevant part of the specifications (Section 12.4)

mongsim commented 5 years ago

Hello Torbjorn,

Thank you for your reply.

I am looking for you git site, l might have lost it. Can send me your git site address.

Thank you,

Mong

Sent from my T-Mobile 4G LTE Device

-------- Original message -------- From: Torbjørn notifications@github.com Date: 3/4/19 04:56 (GMT-07:00) To: riscv/riscv-tests riscv-tests@noreply.github.com Cc: mongsim mong_sim@hotmail.com, Author author@noreply.github.com Subject: Re: [riscv/riscv-tests] How to compile the test code dot S (#168)

I don't know, sorry. Haven't really worked enough with the C extension to be familiar with it, then only thing I can recommend is to read the relevant part of the specificationshttps://riscv.org/specifications/ (Section 12.4)

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHubhttps://github.com/riscv/riscv-tests/issues/168#issuecomment-469226678, or mute the threadhttps://github.com/notifications/unsubscribe-auth/AFbuSPvEN4_Wg6C2jMapAdLVm5K4nTgKks5vTQnxgaJpZM4XzyEb.