search

riscv-software-src / riscv-tools

RISC-V Tools (ISA Simulator and Tests)
1.13k stars 446 forks source link

SPIKE does not generate illegal instruction exception for c.sxxi instructions encoded with zero shift amount #183

Closed deepsrc closed 6 years ago

deepsrc commented 6 years ago

One of our directed tests is failing on SPIKE. It is not detecting the half-word 0x8601 (i.e. c.srai encoded with zero shift amount) as an illegal instruction. According to the RISC-V spec, shift amount of 0 is illegal for c.slli, c.srai and c.srli instructions in RV32C.

The same test when executed on PULPino runs alright.

aswaterman commented 6 years ago

Feel free to make a pull request against riscv-isa-sim to address this problem.

deepsrc commented 6 years ago

Just submitted a pull request. I have tested the changes. They are working fine now.

aswaterman commented 6 years ago

Thanks