The default C (compressed) extension does not contain many instructions that deal with floating point registers so I am trying to create my own. I am following the steps from here: https://nitish2112.github.io/post/adding-instruction-riscv/ but I am getting an error:
"Assembler messages:
Error: internal: bad RISC-V opcode (bits 0xffffffffffff0400 undefined): c.fadd.d CD,Cs,CT
Fatal error: Broken assembler. No assembly attempted."
These are the steps I am doing:
1) Write "c.fadd.d 1..0=3 15..13=4 12..11=0 10..2=ignore" in riscv-opcodes/opcodes-rvc
3)Adding the two lines
"#define MATCH_C_FADD_D 0x8003
define MASK_C_FADD_D 0xf803"
in
"riscv-gnu-toolchain/riscv-binutils-gdb/include/opcode/riscv-opc.h"
4)Adding the line
"{"c.fadd.d", "C", "CD,Cs,CT", MATCH_C_FADD_D, MASK_C_FADD_D, match_opcode, 0 },"
in
"riscv-gnu-toolchain/riscv-binutils-gdb/opcodes/riscv-opc.c "
The default C (compressed) extension does not contain many instructions that deal with floating point registers so I am trying to create my own. I am following the steps from here: https://nitish2112.github.io/post/adding-instruction-riscv/ but I am getting an error:
"Assembler messages: Error: internal: bad RISC-V opcode (bits 0xffffffffffff0400 undefined): c.fadd.d CD,Cs,CT Fatal error: Broken assembler. No assembly attempted."
These are the steps I am doing: 1) Write "c.fadd.d 1..0=3 15..13=4 12..11=0 10..2=ignore" in riscv-opcodes/opcodes-rvc
2)Running command "cat opcodes-pseudo opcodes opcodes-rvc opcodes-rvc-pseudo opcodes-custom | ./parse-opcodes -c > ~/temp.h"
3)Adding the two lines "#define MATCH_C_FADD_D 0x8003
define MASK_C_FADD_D 0xf803"
in "riscv-gnu-toolchain/riscv-binutils-gdb/include/opcode/riscv-opc.h"
4)Adding the line "{"c.fadd.d", "C", "CD,Cs,CT", MATCH_C_FADD_D, MASK_C_FADD_D, match_opcode, 0 }," in "riscv-gnu-toolchain/riscv-binutils-gdb/opcodes/riscv-opc.c "
5)Running build.sh
What am I doing wrong?