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riscv-software-src / riscv-tools

RISC-V Tools (ISA Simulator and Tests)
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Confused with memory-mapped registers #297

Open mayeths opened 4 years ago

mayeths commented 4 years ago

Hi I'm quite new to risc-v and read the unprivileged & privileged specs on riscv.org these days, but now I'm confused with the machine timer registers (section 3.1.10 of privileged spec, relevant issue is #139). It seems that the mtime and mtimecmp are the only memory-mapped registers, but I cannot find their address. Where are they?

Another question is, are there any other memory-mapped registers like mtime and mtimecmp? If answer is no, why we map these two registers into memory instead of using CSR address?

jim-wilson commented 4 years ago

mtime and mtimecmp are CSRs. On rocket-chip and related designs, these CSRs are implemented by using memory mapped I/O, and having a trap handler that redirects accesses to these CSRs to the memory mapped I/O locations. This has something to do with making the design simpler by keeping the real time clock outside the cpu core. Shrug, I'm not a hardware guy. Anyways, since this is a target issue, not a RISC-V ISA issue, you need to check the target specific docs. I don't know about rocket-chip specifically, but some SiFive parts are based on rocket-chip, e.g. the 3 and 5 series parts have the same issue, and the address of these registers can be found in the SiFive docs for these parts. If you have a different target, then you need to find the docs for that target.