Open atsushi-shinbo-esoltrinity opened 6 days ago
This probably isn't the best place for this question, which seeks clarification of ISA content. This project is really about quantifying that content into a machine-readable database.
I suggest posted to the "ISA-dev" mailing list: https://groups.google.com/u/0/a/groups.riscv.org/g/isa-dev.
Current value and location
https://github.com/riscv-software-src/riscv-unified-db/blob/c7a9658554dbb2c627387902a44b8bb0ed605aef/arch/csr/satp.yaml#L46-L47
https://github.com/riscv-software-src/riscv-unified-db/blob/c7a9658554dbb2c627387902a44b8bb0ed605aef/arch/csr/satp.yaml#L64-L65
Expected value
I would like to ask for clarification of the above statement.
The privilege spec version 20240411 makes the following two statements regarding changes to satp:
I think
"Note that writing satp does not imply any ordering constraints between page-table updates and subsequent address translations, nor does it imply any invalidation of address-translation caches"
is conflicted with the statements in riscv-unified-db above.I interpret this to mean that turning mapping off by switching to bare mode takes effect immediately, i.e. it disables the mapping without a fence, but then switching back to a non-bare mode enables mapping while retaining the state that existed before it was switched to bare.
In general, the software has to execute SFENCE.VMA explicitly when changing satp CSR, i.e. no implicit TLB flush is performed when changing satp.ASID and satp.PPN. However, the RISC-V privilege spec does not describe the implicit SFENCE.VMA when changing satp.MODE from/to Bare.
So, I want to clarify this.