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riscv-verification / RVVI

RISC-V Verification Interface
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Usage of csr_wb, csr? #8

Open Silabs-ArjanB opened 2 years ago

Silabs-ArjanB commented 2 years ago

https://github.com/riscv-verification/RVVI/tree/main/RVVI-VLG states:

csr_wb, csr

If the bit position within csr_wb is true, then a the position indicates a write into csr, eg if csr_wb=0x1, then the ustatus register (address 0x000) has been written. If csr_wb=(1<<4 | 1<<0) then address 0x004 and 0x001 have been written concurrently csr_wb=0x0 indicates no written csr.

Are these used as well to report the side effects of taken interrupts?

eroom1966 commented 2 years ago

Yes, that is the intention, so for example mcause, mepc can be updated simultaneously