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riscv / learn

Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.
https://riscv.org/
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QtRvSim - RISC-V CPU Simulator with Cache and Pipeline Visualization #12

Closed ppisa closed 10 months ago

ppisa commented 10 months ago

Resource Title

QtRvSim - RISC-V CPU Simulator with Cache and Pipeline Visualization

Resource Description

QtRvSim is educational simulator with pipeline and cache visualization (RV32IMA/RV64IMA). It supports even M-mode ecalls, ACLINT MTIMER, MSWI, SSWI, related CSR registers, serial port Rx and Tx interrupts and more. The project page https://github.com/cvut/qtrvsim/ provides links to GNU/Linux, Mac OS and Windows native binaries. Online version and related courses materials are available at https://comparch.edu.cvut.cz/ . It provides enough subsystems to run, port or implement a simple (no memory protection or paging; M-mode only) operating system with preemptive multitasking.

Resource Link

https://github.com/cvut/qtrvsim

Required Background (Optional)

Basic or intermediate, ideal companion tool to Computer Organization and Design RISC-V edition: The Hardware Software Interface textbook.

Additional Details (Optional)

Probably fits well into Visual Tools section discussed in #9

KuthumiPepple commented 10 months ago

Thanks for your contribution. I have just added a new Softwares and Tools category, I will include this resource there.