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Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.
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[New RISC-V Tutorial Resource] - Building a RISC-V CPU core, a free edx couse. #20

Closed Shreesh-Kulkarni closed 8 months ago

Shreesh-Kulkarni commented 9 months ago

Resource Title

Building a RISC-V CPU core - Steve Hoover

Resource Description

This free EdX course by Steve Hoover (founder of Redwood EDA) is a great way for a beginner to get started with digital logic design and basic RISC-V microarchitecture design with the help of modern, freely available open source tools such as the Makerchip IDE all from the convenience of your browser. This course provides a hands on experience with the RISC-V ISA and modern open-source logic design tools which utilize the features of a powerful and emerging HDL, Transaction-Level Verilog, designed by Redwood EDA.

Resource Link

Edx Course Link

Required Background (Optional)

No prerequisites required, this course covers all the basics from scratch, although an introductory knowledge on what RISC-V is would be helpful.

Additional Details (Optional)

This course is a beginner level course, it's best suited for enthusiasts with minimal exposure to Digital Design and Computer Architecture.

algorhtym commented 8 months ago

Thank you for your contribution. This is now added as a beginner level resource to the repository.