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Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.
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[New RISC-V Tutorial Resource] - NEORV32, an open-source RISC-V microcontroller #21

Closed stnolting closed 9 months ago

stnolting commented 10 months ago

Resource Title

NEORV32

Resource Description

A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. The project is highly documented, powered by a nice community, includes software examples, demo FPGA setups and targets FPGA/RISC-V starters as well as advanced users.

Resource Link

https://github.com/stnolting/neorv32

Required Background (Optional)

If further information is required I'm happy to provide it :wink:

Additional Details (Optional)

RISC-V enthusiast and community member having +4 years of hobby and professional RISC-V experience in academia and research. The NEORV32 processor has already been incorporated into commercial products as well as several research projects (see Google scholar). The project is listed in the RISC-V architecture ID list, the RISC-V Exchange data base and also in RISC-V Landscape.

algorhtym commented 9 months ago

Thank you for your contribution. This is now added to the repository as an open source implementation.

stnolting commented 9 months ago

Thank you very much! :)