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[New RISC-V Tutorial Resource] - RVfpga 3.0 #22

Closed danidep02 closed 9 months ago

danidep02 commented 10 months ago

Resource Title

RVfpga 3.0: Understanding Computer Architecture

Resource Description

The RVfpga Course in Computer Architecture provides hands-on understanding of a commercial RISC-V processor, RISC-V SoC, and the RISC-V ecosystem. Specifically, the RVfpga v3.0 course shows how to target a VeeR EL2 and a VeeR EH1 based system-on-chip (SoC) to 3 different FPGA boards: the Digilent Basys 3 board ($124 academic price), the Real Digital Boolean board ($74 academic price), and the Digilent Nexys A7 board ($262 academic price). The course can also be completed only in simulation; for that purpose, several simulation tools are provided which enable the user to simulate the system at different levels: from a Boolean/Nexys A7/Basys 3 virtual board down to the VeeR EH1/EL2 pipeline.

Resource Link

https://university.imgtec.com/rvfpga-el2-v3-0-english-downloads-page/

Required Background (Optional)

Expected Prior Knowledge: – Digital design – High-level programming (preferably C) – Instruction set architecture / assembly programming – Microarchitecture – Memory systems

All this material is covered in Digital Design and Computer Architecture: RISC-V Edition, Harris & Harris, Elsevier 2021.

Additional Details (Optional)

Please contact with Daniel Chaver at dani02@ucm.es for any questions or comments.