[New RISC-V Tutorial Resource] - Hands-on course on designing RV32I Processor

[raulbehl]

Resource Title

Hands-on RISC-V Processor Design

Resource Description

This tutorial offers a deep dive into the world of computer architecture and processor design, with a specific focus on the RISC-V Instruction Set Architecture (ISA). The course covers the following:

• Fundamental concepts of computer architecture and processor design
• Practical exposure to the unprivileged RISC-V Instruction Set Architecture (ISA)
• Learn to design a single-cycle RV32I compliant processor from scratch in SystemVerilog
• Create RISC-V assembly programs and execute them on the designed processor

Resource Link

https://quicksilicon.in/course/riscv

Required Background (Optional)

Some exposure to using SystemVerilog for Design is recommended but not necessary

Additional Details (Optional)

No response

[algorhtym]

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