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2 years ago Cbo.zero, as a form or memory-accessing instruction, is subject to PMAs the same as other load/store instructions. A PMA region may allow or disallow cbo.zero (just like it can allow or disallow various forms of AMOs). In general a PMA-disallowed access results in an Access Fault on the instruction trying to do the disallowed access. If cbo.zero is allowed to a PMA region, then that region's cacheability and ordering attributes apply to cbo.zero (as a form of store operation) similar to how they apply to normal loads and stores.
As far as whether cbo.zero can be implemented as multiple writes, that is allowed - just the same as an existing 4B store instruction is allowed to be implemented, for example, as four 1B writes.
As defined by the spec in Chapter 4.2, cbo.zero is used for a cache block and "Cache-block zero instructions store zeros independently of whether data from the underlying memory locations are cacheable." It's not defined clearly in spec for the operation when its PMA is strong order. Can the implementation generate a Store/AMO access fault directly just like the AMO instruction set. Otherwise, it becomes complicated. For example, the CPU should generate and send out at least four transactions for one cbo.zero instruction to write a total cacheline in AMBA AXI protocol. Moreover, how about the non-cacheable memory attribute?