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riscv / riscv-CMOs

https://jira.riscv.org/browse/RVG-59
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Does the prefetch.r instruction support specific cache levels? #63

Closed Kepontry closed 1 year ago

Kepontry commented 1 year ago

Prefetch instructions in X86 isa, such as prefetcht0, support prefetching the data into specific cache levels. Does the prefetch.r instruction in RISC-V support similar functions?

ved-rivos commented 1 year ago

Please see - https://github.com/riscv/riscv-isa-manual/blob/main/src/zihintntl.adoc regards ved

On Sun, Jun 25, 2023 at 10:08 AM Jiapeng Zhou @.***> wrote:

Prefetch instructions in X86 isa, such as prefetcht0, support prefetching the data into specific cache levels. Does the prefetch.r instruction in RISC-V support similar functions?

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Kepontry commented 1 year ago

Thanks a lot.